Github 上有哪些优秀的 VHDL/Verilog/FPGA 项目

1450

676

33

1 year, 1 month ago

e200_opensource/1

The Ultra-Low Power RISC Core

1371

362

27

5 months ago

picorv32/2

PicoRV32 – A Size-Optimized RISC-V CPU

1157

399

23

10 months ago

wujian100_open/3

IC design and development should be faster，simpler and more reliable

936

371

176

2 years ago

hw/4

RTL, Cmodel, and testbench for NVDLA

930

61

2

1 year, 6 months ago

amiga2000-gfxcard/5

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

886

119

7

20 hours ago

darkriscv/6

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

618

160

10

3 years ago

miaow/7

An open source GPU based off of the AMD Southern Islands ISA.

615

921

25

a day ago

hdl/8

HDL libraries and projects

581

70

0

2 months ago

zipcpu/9

A small, light weight, RISC CPU soft core

573

199

16

16 hours ago

verilog-ethernet/10

Verilog Ethernet components for FPGA implementation

547

194

30

2 years ago

oh/11

Verilog library for ASIC and FPGA designers

487

426

38

23 days ago

uhd/12

The USRP™ Hardware Driver Repository

475

87

11

2 hours ago

corundum/13

Open source, high performance, FPGA-based NIC

409

192

6

1 year, 10 months ago

ODriveHardware/14

High performance motor control

400

138

4

5 months ago

open-fpga-verilog-tutorial/15

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

387

86

38

3 days ago

sd2snes/16

SD card based multi-purpose cartridge for the SNES

384

149

1

3 years ago

mips-cpu/17

MIPS CPU implemented in Verilog

360

71

0

9 months ago

LeFlow/18

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

317

116

24

2 months ago

mor1kx/19

mor1kx – an OpenRISC 1000 processor IP core

294

139

0

5 years ago

FPGA-Imaging-Library/20

An open source library for image processing on FPGA.

289

151

37

4 years ago

riffa/21

The RIFFA development repository

286

48

11

4 months ago

riscv-formal/22

RISC-V Formal Verification Framework

270

96

0

2 years ago

verilog/23

Repository for basic (and not so basic) Verilog blocks with high re-use potential

269

89

7

1 year, 4 months ago

icezum/24

�� IceZUM Alhambra: an Arduino-like Open FPGA electronic board

267

124

14

8 years ago

netfpga/25

NetFPGA 1G infrastructure and gateware

255

43

8

4 days ago

serv/26

SERV – The SErial RISC-V CPU

252

86

4

a month ago

verilog-axi/27

Verilog AXI components for FPGA implementation

250

37

8

3 months ago

VerilogBoy/28

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

243

27

7

1 year, 4 months ago

Project-Zipline/29

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

235

114

6

6 years ago

FPGA-Litecoin-Miner/30

A litecoin scrypt miner implemented with FPGA on-chip memory.

213

54

2

2 years ago

zet/31

Open source implementation of a x86 processor

210

96

16

2 years ago

convolution_network_on_FPGA/32

CNN acceleration on virtex-7 FPGA with verilog HDL

209

20

65

7 months ago

ucr-eecs168-lab/33

The lab schedules for EECS168 at UC Riverside

198

85

2

3 months ago

cores/34

Various HDL (Verilog) IP Cores

194

21

20

1 year, 6 days ago

spispy/35

An open source SPI flash emulator and monitor

193

37

1

3 years ago

ridecore/36

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

190

53

32

24 days ago

OpenROAD/37

OpenROAD’s unified application implementing an RTL-to-GDS Flow

190

69

0

a month ago

basic_verilog/38

Must-have verilog systemverilog modules

190

46

1

5 months ago

riscv/39

RISC-V CPU Core (RV32IM)

189

30

4

6 days ago

Flute/40

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

184

69

13

11 months ago

fpu/41

synthesiseable ieee 754 floating point library in verilog

183

49

22

8 years ago

fpga_nes/42

FPGA-based Nintendo Entertainment System Emulator

181

62

1

4 years ago

verilog-6502/43

A Verilog HDL model of the MOS 6502 CPU

179

35

13

a month ago

Piccolo/44

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

174

64

6

16 hours ago

verilog-pcie/45

Verilog PCI express components

173

58

10

5 months ago

Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/46

Verilog Generator of Neural Net Digit Detector for FPGA

168

7

1

1 year, 9 months ago

fpga-chip8/47

CHIP-8 console on FPGA

165

169

1

4 months ago

fpga/48

The USRP™ Hardware Driver FPGA Repository

163

26

5

2 years ago

TinyFPGA-B-Series/49

Open source design files for the TinyFPGA B-Series boards.

162

21

0

6 years ago

ez8/50

The Easy 8-bit Processor

156

37

94

6 hours ago

basejump_stl/51

BaseJump STL: A Standard Template Library for SystemVerilog

155

10

0

11 months ago

fpg1/52

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

153

32

14

6 hours ago

openlane/53

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

150

52

1

3 years ago

sdram-controller/54

Verilog SDRAM memory controller

146

47

3

10 months ago

AccDNN/55

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

146

59

2

1 year, 4 months ago

verilog-i2c/56

Verilog I2C interface for FPGA implementation

145

65

0

2 months ago

Kryon/57

FPGA,Verilog,Python

142

61

4

1 year, 6 months ago

verilog-uart/58

Verilog UART

137

53

2

6 months ago

sha256/59

Hardware implementation of the SHA-256 cryptographic hash function

137

50

3

2 years ago

CNN-FPGA/60

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

133

20

1

9 days ago

wb2axip/61

Bus bridges and other odds and ends

127

102

114

3 months ago

black-parrot/62

A Linux-capable host multicore for and by the world

124

38

0

6 years ago

milkymist/63

SoC design for Milkymist One – LM32, DDR SDRAM, 2D TMU, PFPU

123

24

0

1 year, 10 months ago

SimpleVOut/64

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

122

23

4

11 months ago

FPGA-peripherals/65

�� ❄️ Collection of open-source peripherals in Verilog

119

41

5

1 year, 2 months ago

Tang_E203_Mini/66

LicheeTang 蜂鸟E203 Core

118

66

3

3 years ago

FPGA_Based_CNN/67

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

118

44

2

a month ago

SCALE-MAMBA/68

Repository for the SCALE-MAMBA MPC system

116

25

0

a month ago

wbuart32/69

A simple, basic, formally verified UART controller

113

41

3

6 years ago

fpganes/70

NES in Verilog

113

41

19

11 months ago

open-register-design-tool/71

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

110

20

5

1 year, 6 months ago

DisplayPort_Verilog/72

A Verilog implementation of DisplayPort protocol for FPGAs

110

51

0

27 days ago

openwifi-hw/73

FPGA/hardware design of openwifi

110

77

16

2 years ago

orpsoc-cores/74

Core description files for FuseSoC

108

57

0

5 days ago

aes/75

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

107

41

0

22 days ago

schoolMIPS/76

CPU microarchitecture, step by step

106

58

5

a month ago

openofdm/77

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

106

26

1

23 days ago

iceGDROM/78

An FPGA based GDROM emulator for the Sega Dreamcast

105

10

0

2 years ago

vm80a/79

i8080 precise replica in Verilog, based on reverse engineering of real die

102

30

3

a day ago

nandland/80

All code found on nandland is here. underconstruction.gif

101

27

0

2 years ago

mriscv/81

A 32-bit Microcontroller featuring a RISC-V core

100

43

1

8 years ago

fft-dit-fpga/82

Verilog module for calculation of FFT.

98

14

3

a month ago

DreamcastHDMI/83

Dreamcast HDMI

98

26

2

6 months ago

RePlAce/84

RePlAce global placement tool

97

68

4

3 years ago

Hardware-CNN/85

A convolutional neural network implemented in hardware (verilog)

97

29

2

2 years ago

Single_instruction_cycle_OpenMIPS/86

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

97

70

4

7 years ago

uvm_axi/87

uvm AXI BFM(bus functional model)

96

16

0

19 days ago

a2o/88

None

96

13

58

1 year, 10 months ago

spatial-lang/89

Spatial: “Specify Parameterized Accelerators Through Inordinately Abstract Language”

95

17

17

a day ago

livehd/90

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

95

19

3

5 months ago

biriscv/91

32-bit Superscalar RISC-V CPU

95

12

1

2 months ago

cpu11/92

Revengineered ancient PDP-11 CPUs, originals and clones

94

61

1

4 years ago

or1200/93

OpenRISC 1200 implementation

93

20

3

11 days ago

warp-v/94

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

93

17

1

5 years ago

oldland-cpu/95

Oldland CPU – a 32-bit RISC FPGA CPU including RTL + tools

92

29

1

3 years ago

kamikaze/96

Light-weight RISC-V RV32IMC microcontroller core.

90

18

0

3 years ago

archexp/97

浙江大学计算机体系结构课程实验

90

12

3

10 months ago

panologic-g2/98

Pano Logic G2 Reverse Engineering Project

86

29

2

2 months ago

apple-one/99

An attempt at a small Verilog implementation of the original Apple 1 on an FPGA

85

23

0

10 months ago

mips32-cpu/100

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

85

14

2

11 months ago

raven-picorv32/101

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

86

22

1

28 days ago

ice40-playground/102

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

84

9

1

1 year, 10 months ago

NeoGeoFPGA-sim/103

Simulation only cartridge NeoGeo hardware definition

83

29

0

3 days ago

ivtest/104

Regression test suite for Icarus Verilog.

82

76

0

2 years ago

FPGA-CNN/105

FPGA implementation of Cellular Neural Network (CNN)

82

16

3

5 years ago

NeoGeoHDMI/106

Verilog project that takes the digital video and audio from a Neo Geo MVS before going through the DACs and outputs the signals over HDMI

81

5

0

a month ago

vgasim/107

A Video display simulator

80

36

8

1 year, 3 months ago

mipsfpga-plus/108

MIPSfpga+ allows loading programs via UART and has a switchable clock

80

16

0

3 months ago

openarty/109

An Open Source configuration of the Arty platform

79

29

1

7 years ago

Xilinx-Serial-Miner/110

Bitcoin miner for Xilinx FPGAs

79

10

4

13 days ago

n64rgb/111

Everything around N64 and RGB

79

35

8

10 months ago

Tang_FPGA_Examples/112

LicheeTang FPGA Examples

78

10

1

3 months ago

lpc_sniffer_tpm/113

A low pin count sniffer for ICEStick – targeting TPM chips

78

20

15

2 years ago

c65gs/114

FPGA-based C64 Accelerator / C65 like computer

78

8

1

9 years ago

Homotopy/115

Homotopy theory in Coq.

78

8

0

2 years ago

iCE40/116

Lattice iCE40 FPGA experiments – Work in progress

78

18

1

9 months ago

usbcorev/117

A full-speed device-side USB peripheral core written in Verilog.

78

34

18

8 days ago

Hermes-Lite2/118

A second generation low-cost amateur HF software defined radio transceiver.

77

26

0

9 months ago

NaiveMIPS-HDL/119

Naïve MIPS32 SoC implementation

77

24

0

5 years ago

lm32/120

LatticeMico32 soft processor

77

18

3

3 months ago

tinyfpga_bx_usbserial/121

USB Serial on the TinyFPGA BX

76

23

0

5 years ago

cpu/122

A very primitive but hopefully self-educational CPU in Verilog

76

44

65

8 hours ago

fomu-workshop/123

Support files for participating in a Fomu workshop

76

7

3

5 hours ago

jt12/124

FM sound source written in Verilog, fully compatible with YM2612, YM3438 (JT12), YM2203 (JT03) and YM2610 (JT10)

75

11

3

4 years ago

fpgaboy/125

Implementation Nintendo’s GameBoy console on an FPGA

75

7

4

a month ago

usb3_pipe/126

USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

75

43

3

7 years ago

Icarus/127

DUAL Spartan6 Development Platform

74

11

1

4 months ago

Toooba/128

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

74

7

1

5 months ago

antikernel/129

The Antikernel operating system project

72

18

0

a month ago

icebreaker-examples/130

This repository contains small example designs that can be used with the open source icestorm flow.

70

9

0

4 years ago

PonyLink/131

A single-wire bi-directional chip-to-chip interface for FPGAs

70

12

1

3 days ago

Radioberry-2.x/132

Ham Radio hat for Raspberry PI

70

12

0

7 months ago

agc_simulation/133

Verilog simulation files for a replica of the Apollo Guidance Computer

69

7

1

6 months ago

display_controller/134

FPGA display controller with support for VGA, DVI, and HDMI.

69

19

7

4 months ago

ice40_examples/135

Public examples of ICE40 HX8K examples using Icestorm

68

30

24

4 days ago

ao486_MiSTer/136

ao486 port for MiSTer

68

46

4

6 years ago

DSLogic-hdl/137

An open source FPGA design for DSLogic

67

7

1

18 hours ago

icestation-32/138

Compact FPGA game console

67

41

18

2 months ago

Genesis_MiSTer/139

Sega Genesis for MiSTer

67

27

0

1 year, 8 months ago

PASC/140

Parallel Array of Simple Cores. Multicore processor.

66

28

0

3 months ago

Verilog-Practice/141

HDLBits website practices & solutions

65

4

4

a month ago

RISCBoy/142

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

65

8

8

2 months ago

xcrypto/143

XCrypto: a cryptographic ISE for RISC-V

64

28

8

1 year, 1 month ago

c5soc_opencl/144

DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

63

17

2

1 year, 9 months ago

ZAP/145

ZAP is a pipelined ARMv4T architecture compatible processor with cache and MMU.

62

11

0

4 years ago

cpus-caddr/146

FPGA based MIT CADR lisp machine – rewritten in modern verilog – boots and runs

62

32

1

2 years ago

zynq-axis/147

Hardware, Linux Driver and Library for the Zynq AXI DMA interface

62

14

5

1 year, 1 month ago

Reindeer/148

PulseRain Reindeer – RISCV RV32I[M] Soft CPU

61

9

3

30 days ago

jt_gng/149

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts’n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando and Vulgus.

60

14

0

1 year, 3 days ago

MobileNet-in-FPGA/150

Generator of verilog description for FPGA MobileNet implementation

59

16

6

8 months ago

Haasoscope/151

Docs, design, firmware, and software for the Haasoscope

58

13

3

8 years ago

ao68000/152

The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.

58

22

18

a day ago

Minimig-AGA_MiSTer/153

None

58

7

0

3 years ago

FPGA-TX/154

FPGA based transmitter

58

8

0

2 years ago

toygpu/155

A simple GPU on a TinyFPGA BX

57

8

1

11 months ago

Riscy-SoC/156

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

57

9

0

1 year, 1 month ago

MIPS-pipeline-processor/157

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

56

23

1

2 years ago

VidorFPGA/158

repository for Vidor FPGA IP blocks and projects

55

30

19

8 days ago

NeoGeo_MiSTer/159

NeoGeo for MiSTer

54

23

2

5 months ago

SD-card-controller/160

WISHBONE SD Card Controller IP Core

54

7

13

1 year, 3 months ago

Neogeo_MiSTer_old/161

SNK NeoGeo core for the MiSTer platform

54

13

0

4 months ago

hardenedlinux_profiles/162

It contains hardenedlinux community documentation.

53

24

0

a month ago

cdbus_ip/163

CDBUS Protocol and the IP Core for FPGA users

53

18

0

2 years ago

clacc/164

Deep Learning Accelerator (Convolution Neural Networks)

52

25

0

a month ago

timetoexplore/165

Source code to accompany https://timetoexplore.net

52

13

0

4 years ago

fpga-md5-cracker/166

A 64-stage pipelined MD5 implementation written in verliog. Runs reliably on a DE0-Nano at 100mhz, computing 100 million hashes per second.

52

17

14

1 year, 28 days ago

alpha-release/167

Builds, flow and designs for the alpha release

52

9

1

7 months ago

ice40_ultraplus_examples/168

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

51

30

0

7 years ago

uart/169

Verilog UART

51

11

0

1 year, 5 months ago

MARLANN/170

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

51

4

2

10 months ago

ay-3-8910_reverse_engineered/171

The reverse-engineered AY-3-8910 chip. Transistor-level schematics, verilog model and a testbench with tools, that can render register dump files into .flac soundtrack.

50

7

0

1 year, 4 months ago

up5k_basic/172

A small 6502 system with MS BASIC in ROM

50

21

1

10 months ago

opencpi/173

Open Component Portability Infrastructure

50

20

51

5 days ago

bsg_manycore/174

Tile based architecture designed for computing efficiency, scalability and generality

50

22

0

2 years ago

verilog-lfsr/175

Fully parametrizable combinatorial parallel LFSR/CRC module

50

47

5

2 years ago

Convolutional-Neural-Network/176

Implementation of CNN using Verilog

50

13

0

1 year, 9 months ago

VexRiscvSoftcoreContest2018/177

None

50

28

34

4 years ago

minimig-mist/178

Minimig for the MiST board

49

28

0

a month ago

cdpga/179

FPGA core boards / evaluation boards based on CDCTL hardware

49

9

0

1 year, 11 months ago

riscv/180

Verilog implementation of a RISC-V core

48

11

3

19 days ago

aib-phy-hardware/181

Advanced Interface Bus (AIB) die-to-die hardware open source

48

2

0

1 year, 6 months ago

soc/182

An experimental System-on-Chip with a custom compiler toolchain.

47

15

0

6 years ago

verilog_fixed_point_math_library/183

Fixed Point Math Library for Verilog

46

40

1

a month ago

Practical-UVM-Step-By-Step/184

This is the main repository for all the examples for the book Practical UVM

46

22

3

3 years ago

digital-servo/185

NIST digital servo: an FPGA based fast digital feedback controller

45

3

1

3 years ago

21FX/186

A bootloader for the SNES console

46

14

0

2 years ago

hyperram/187

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

46

20

2

1 year, 4 days ago

daisho/188

Test of the USB3 IP Core from Daisho on a Xilinx device

45

14

1

8 months ago

aib-phy-hardware/189

None

45

9

1

2 years ago

RISC-V-CPU/190

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

45

10

1

1 year, 5 months ago

up5k/191

Upduino v2 with the ice40 up5k FPGA demos

45

33

1

5 years ago

mips32r1_xum/192

A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old University of Utah XUM archive)

44

3

0

21 days ago

wbscope/193

A wishbone controlled scope for FPGA’s

44

26

2

6 years ago

beagle/194

BeagleBone HW, SW, & FPGA Development

44

3

0

2 years ago

collection-iPxs/195

Icestudio Pixel Stream collection

44

14

0

2 years ago

SoftMC/196

SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. The design, the interface, and its capabilities and limitations are discussed in our HPCA 2017 paper: “SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies” https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf

44

17

2

2 years ago

chiphack/197

Repository and Wiki for Chip Hack events.

44

5

0

2 months ago

XilinxUnisimLibrary/198

None

44

15

3

8 years ago

ORGFXSoC/199

An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)

44

7

47

21 days ago

rigel/200

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

43

22

8

3 years ago

nysa-sata/201

None

44

20

0

2 years ago

TOE/202

TCP Offload Engine

43

24

0

25 days ago

async_fifo/203

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

43

17

0

2 years ago

MIPS/204

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

43

4

0

1 year, 5 months ago

rt/205

A Full Hardware Real-Time Ray-Tracer

42

4

1

8 months ago

flickerfixer/206

An open source flicker fixer for Amiga 500/2000

41

37

1

1 year, 3 months ago

AlteraDE2Labs_Verilog/207

My solutions to Alteras example labs

41

15

0

5 years ago

Verilog-caches/208

Various caches written in Verilog-HDL

41

10

0

3 years ago

mc6809/209

Cycle-Accurate MC6809/E implementation, Verilog

40

7

0

4 years ago

MAM65C02-Processor-Core/210

Microprogrammed 65C02-compatible Processor Core for FPGAs (Verilog-2001)

40

21

1

a month ago

libsystemctlm-soc/211

SystemC/TLM-2.0 Co-simulation framework

40

5

1

1 year, 2 months ago

engine-V/212

SoftCPU/SoC engine-V

40

13

0

4 years ago

yarvi/213

Yet Another RISC-V Implementation

39

7

15

2 days ago

hrm-cpu/214

Human Resource Machine – CPU Design #HRM

39

5

1

2 years ago

lpc_sniffer/215

a low pin count sniffer for icestick

39

8

0

3 months ago

moxie-cores/216

Moxie-compatible core repository

39

3

1

a month ago

iua/217

ice40 USB Analyzer

39

12

0

4 years ago

sds7102/218

A port of Linux to the OWON SDS7102 scope

38

19

1

2 months ago

cnn_hardware_acclerator_for_fpga/219

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

38

10

0

1 year, 5 months ago

Speech256/220

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

38

26

1

1 year, 8 months ago

GNSS_Firehose/221

Wideband front-end digitizer for GPS, GLONASS, Galileo, BeiDou

38

7

1

11 months ago

panologic/222

PanoLogic Zero Client G1 reverse engineering info

37

9

0

1 year, 3 months ago

ctf/223

Stuff from CTF contests

37

30

0

5 years ago

mojo-base-project/224

This is the base project for the Mojo. It should be used as the starting point for all projects.

37

6

0

5 months ago

MIPS48PipelineCPU/225

冯爱民老师《计算机组成原理A》课程设计

37

7

0

3 years ago

mips-cpu/226

A MIPS CPU implemented in Verilog

37

14

0

11 months ago

R8051/227

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

37

12

2

1 year, 4 months ago

Verilog-Projects/228

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

37

10

0

3 months ago

challenges-2020/229

Pwn2Win 2020 Challenges

37

21

2

1 year, 2 months ago

verilog-cam/230

Verilog Content Addressable Memory Module

37

6

2

9 months ago

OpenAmiga500FastRamExpansion/231

4/8 MB Fast RAM Expansion for the Commodore Amiga 500

36

8

2

4 years ago

ACC/232

Apollo CPU Core in Verilog. For learning and having fun with open FPGA

36

7

2

2 years ago

cnnhwpe/233

None

36

12

1

5 months ago

fpga-sdft/234

sliding DFT for FPGA, targetting Lattice ICE40 1k

36

12

0

4 months ago

sha3/235

None

36

9

0

8 years ago

dcpu16/236

Pipelined DCPU-16 Verilog Implementation

35

16

1

2 years ago

ARM7/237

Implemetation of pipelined ARM7TDMI processor in Verilog

35

2

0

2 years ago

vga_to_ascii/238

Realtime VGA to ASCII Art converter

35

29

1

2 years ago

ethernet_10ge_mac_SV_UVM_tb/239

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

35

18

18

17 days ago

MegaCD_MiSTer/240

Mega CD for MiSTer

35

9

0

1 year, 8 months ago

HyperBUS/241

A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs

35

7

9

1 year, 11 months ago

BeagleWire/242

This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017

35

12

0

3 years ago

caribou/243

Caribou: Distributed Smart Storage built with FPGAs

35

4

0

2 years ago

RISC-processor/244

Simple single cycle RISC processor written in Verilog

35

24

3

2 years ago

prog_fpgas/245

The repository for the Verilog code examples and ISE projects that accompany the book Programming FPGAs: Getting Started with Verilog.

35

16

1

5 years ago

minimig-de1/246

Minimig for the DE1 board

34

13

0

7 years ago

Multiplier16X16/247

Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder

34

11

5

5 days ago

mflowgen/248

mflowgen — A Modular ASIC/FPGA Flow Generator

34

11

0

4 months ago

max1000-tutorial/249

Tutorial and example projects for the Arrow MAX1000 FPGA board

34

10

0

9 months ago

icebreaker-workshop/250

iCEBreaker Workshop

34

7

1

2 years ago

BAR-Tender/251

An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver

34

21

3

4 years ago

bch_verilog/252

Verilog based BCH encoder/decoder

33

12

1

8 years ago

vSPI/253

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

33

6

0

28 days ago

rsyocto/254

�� SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

33

19

1

3 years ago

h.265_encoder/255

None

33

7

3

a month ago

iceZ0mb1e/256

FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC

32

13

0

5 years ago

verilog-utils/257

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

32

11

1

12 days ago

fusesoc-cores/258

FuseSoC standard core library

32

5

0

1 year, 4 months ago

fpga-odysseus/259

FPGA Odysseus with ULX3S

32

4

2

3 years ago

Frix/260

IBM PC Compatible SoC for a commercially available FPGA board

32

18

0

2 years ago

mnist_fpga/261

using xilinx xc6slx45 to implement mnist net

32

19

0

1 year, 10 months ago

huaweicloud-fpga/262

The official repository of the HUAWEI CLOUD FPGA Development Kit based on HUAWEI CLOUD FPGA Accelerated Cloud Server.

32

7

0

7 months ago

dpll/263

A collection of phase locked loop (PLL) related projects

31

12

2

6 months ago

h265-encoder-rtl/264

None

31

16

1

17 years ago

8051/265

8051 core

31

18

1

2 years ago

GnuRadar/266

Open-source software defined radar based on the USRP 1 hardware.

31

13

0

2 years ago

robot-arm-v01/267

None

31

2

0

5 years ago

gb/268

The Original Nintendo Gameboy in Verilog

31

8

3

5 months ago

tinyriscv/269

A very simple and easy to understand RISC-V core.

31

6

0

3 years ago

wiki/270

None

31

13

0

7 years ago

fpganes/271

FPGA-based AI for Super Mario Bros. Designed for an Altera DE2

31

10

0

9 months ago

drec-fpga-intro/272

Materials for “Introduction to FPGA and Verilog” at MIPT DREC

30

5

1

5 years ago

oc_jpegencode/273

Fork of OpenCores jpegencode with Cocotb testbench

30

27

0

5 years ago

IPCORE/274

None

30

1

2

10 months ago

spokefpga/275

FPGA Tools and Library

30

26

3

6 years ago

cordic/276

An implementation of the CORDIC algorithm in Verilog.

30

24

0

8 years ago

DDR2_Controller/277

DDR2 memory controller written in Verilog

29

3

0

1 year, 10 months ago

riscv-megaproject/278

A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones

29

2

0

4 years ago

HaSKI/279

Cλash/Haskell FPGA-based SKI calculus evaluator

29

5

0

2 years ago

OpenFPGA/280

OpenFPGA

29

10

3

a month ago

verilog-math/281

Mathematical Functions in Verilog

29

21

0

3 months ago

thinpad_top/282

Project template for Artix-7 based Thinpad board

29

3

0

1 year, 8 months ago

tiny_usb_examples/283

Using the TinyFPGA BX USB code in user designs

29

5

0

2 years ago

screen-pong/284

Pong game in a free FPGA.

29

34

1

5 days ago

oc-accel/285

OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology

29

21

2

4 days ago

blinky/286

Example LED blinking project for your FPGA dev board of choice

28

5

0

2 years ago

DIY_OpenMIPS/287

實作《自己動手寫CPU》書上的程式碼

28

8

3

4 months ago

i3c-slave-design/288

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

28

3

1

12 days ago

VGChips/289

Video Game custom chips reverse-engineered from silicon

28

3

3

4 months ago

observer/290

None

28

10

0

1 year, 2 months ago

csirx/291

Open-source CSI-2 receiver for Xilinx UltraScale parts

28

18

1

7 years ago

Atalanta/292

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

28

10

41

23 days ago

zx-evo/293

TS-Configuration for ZX Spectrum clone named ZX-Evolution

28

3

0

2 years ago

Computer-Architecture-Task-2/294

Riscv32 CPU Project

28

5

2

a day ago

ice-chips-verilog/295

IceChips is a library of all common discrete logic devices in Verilog

28

7

0

2 months ago

first-fpga-pcb/296

FPGA dev board based on Lattice iCE40 8k

28

9

0

4 months ago

MangoMIPS32/297

A softcore microprocessor of MIPS32 architecture.

28

4

0

6 years ago

CPU32/298

Tiny MIPS for Terasic DE0

27

14

0

2 years ago

eddr3/299

mirror of https://git.elphel.com/Elphel/eddr3

27

12

0

4 years ago

yosys-bigsim/300

A collection of big designs to run post-synthesis simulations with yosys

27

12

0

4 years ago

yosys-bigsim/301

A collection of big designs to run post-synthesis simulations with yosys

27

23

3

28 days ago

Menu_MiSTer/302

None

27

12

51

4 months ago

tapasco/303

The Task Parallel System Composer (TaPaSCo)

27

31

0

6 years ago

FPGA_image_processing/304

Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image

27

15

0

8 years ago

verilog-sha256/305

Implementation of the SHA256 Algorithm in Verilog

27

17

0

1 year, 6 months ago

x393/306

mirror of https://git.elphel.com/Elphel/x393

27

17

0

8 years ago

tdc-core/307

A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

27

3

1

4 years ago

RISCV_Piccolo_v1/308

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

27

3

2

3 days ago

QuokkaEvaluation/309

Example projects for Quokka FPGA toolkit

27

9

0

1 year, 4 months ago

BUAA_CO/310

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

26

13

1

1 year, 7 days ago

ethmac/311

Ethernet MAC 10/100 Mbps

26

3

0

2 years ago

s6soc/312

CMod-S6 SoC

26

8

17

8 days ago

symbiflow-examples/313

Examples designs for showing different ways to use SymbiFlow toolchains.

26

5

2

1 year, 9 months ago

iCEstick-UART-Demo/314

This is a simple UART echo test for the iCEstick Evaluation Kit

26

8

0

5 months ago

LUTNet/315

None

26

13

0

4 years ago

peridot/316

‘PERIDOT’ – Simple & Compact FPGA board

26

6

0

2 days ago

trng/317

True Random Number Generator core implemented in Verilog.

26

15

0

7 years ago

rfid-verilog/318

RFID tag and tester in Verilog

25

21

0

5 years ago

CNN_FPGA/319

verilog CNN generator for FPGA

25

3

2

8 months ago

zbasic/320

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

25

16

0

3 years ago

HitchHike/321

None

25

8

0

6 years ago

vj-uart/322

Virtual JTAG UART for Altera Devices

25

13

1

2 years ago

openmsp430/323

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.

25

9

0

4 days ago

myslides/324

Collection of my presentations

25

5

2

8 months ago

datc_robust_design_flow/325

DATC Robust Design Flow.

25

2

4

11 months ago

quark/326

Stack CPU �� Work In Progress ��

25

14

0

5 years ago

Video-and-Image-Processing-Design-Using-FPGAs/327

Video and Image Processing

25

10

0

3 years ago

ECE1373_2016_hft_on_fpga/328

High Frequency Trading using Vivado HLS

25

6

0

2 months ago

jt49/329

Verilog clone of YM2149

25

13

1

6 years ago

ddk-fpga/330

FPGA HDL Sources.

25

21

0

7 years ago

opensketch/331

simulation and netfpga code

25

2

1

1 year, 3 months ago

icebreaker-candy/332

Eye candy from an iCEBreaker FPGA and a 64×64 LED panel

25

18

0

2 years ago

OV7670-Verilog/333

Verilog modules required to get the OV7670 camera working

25

0

0

6 months ago

gameboy-fpga-cartridge/334

None

24

9

1

3 years ago

ocpi/335

Semi-private RTL development upstream of OpenCPI – this is not the OpenCPI repo!

24

9

0

7 years ago

lsasim/336

Educational load/store instruction set architecture processor simulator

24

18

0

3 years ago

fpga_design/337

这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统

24

4

1

1 year, 9 months ago

Lichee-Tang/338

Lichee Tang FPGA board examples

24

5

0

6 years ago

LVDS-7-to-1-Serializer/339

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

24

20

7

6 years ago

MM/340

Miner Manager

24

11

0

4 years ago

nfmac10g/341

Open source 10 Gigabit Ethernet MAC core compatible with Xilinx’s non-free 10GMAC

24

4

3

1 year, 3 months ago

v-regex/342

A simple regex library for V

24

4

0

4 months ago

EDN8-PRO/343

EverDrive N8 PRO dev sources

23

6

0

10 months ago

fftdemo/344

A demonstration showing how several components can be compsed to build a simulated spectrogram

23

4

4

7 months ago

A500-8MB-FastRAM/345

8MB FastRAM Board for the Amiga 500 & Amiga 500+

23

7

0

6 years ago

aoOCS/346

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig – it is a new and independent Amiga OCS implementation.

23

17

0

3 years ago

fast/347

FAST

23

4

0

10 months ago

hackaday_supercon_2019_logic_noise_FPGA_workshop/348

Hackaday Supercon 2019 Logic Noise Badge Workshop

23

12

2

4 years ago

FPU/349

IEEE 754 floating point unit in Verilog

23

7

0

8 years ago

aemb/350

Multi-threaded 32-bit embedded core family.

23

11

0

2 years ago

workshops/351

❄️ �� Workshops with Icestudio and the IceZUM Alhambra board

23

4

0

4 months ago

poyo-v/352

Open source RISC-V IP core for FPGA/ASIC design

23

14

0

10 years ago

sparc64soc/353

OpenSPARC-based SoC

23

2

1

a month ago

basic-ecp5-pcb/354

None

23

9

40

3 days ago

mantle/355

mantle library

23

13

0

4 years ago

AES-FPGA/356

AES加密解密算法的Verilog实现

23

15

20

3 years ago

RetroCade_Synth/357

RetroCade Synth – C64 SID, YM2149, and POKEY audio chips with MIDI interface.

23

6

2

2 months ago

benchmarks/358

EPFL logic synthesis benchmarks

23

11

0

6 months ago

sha1/359

Verilog implementation of the SHA-1 cryptgraphic hash function

23

8

3

3 years ago

Nitro-Parts-lib-Xilinx/360

This is mainly a simulation library of xilinx primitives that are verilator compatible.

23

10

2

2 years ago

CNN_VGG19_verilog/361

Convolution Neural Network of vgg19 model in verilog

23

7

0

1 year, 4 months ago

Open-FPGA/362

Devotes to open source FPGA

22

10

0

4 years ago

FFT_Verilog/363

FFT implement by verilog_测试验证已通过

22

3

0

1 year, 4 months ago

thunderclap-fpga-arria10/364

Thunderclap hardware for Intel Arria 10 FPGA

22

8

2

1 year, 3 months ago

Posit-HDL-Arithmetic/365

Universal number Posit HDL Arithmetic Architecture generator

22

25

2

1 year, 1 month ago

block-nvdla-sifive/366

None

22

9

0

4 years ago

stx_cookbook/367

Altera Advanced Synthesis Cookbook 11.0

22

19

1

1 year, 6 days ago

LimeSDR-PCIe_GW/368

Altera Cyclone IV FPGA project for the PCIe LimeSDR board

22

7

1

7 months ago

Tang-Nano-examples/369

Tang-Nano-examples

22

12

0

4 years ago

FPGA_Ultrasound/370

CMU 18545 FPGA project — Multi-channel ultrasound data acquisition and beamforming system.

22

12

2

1 year, 11 months ago

ARM9-compatible-soft-CPU-core/371

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

23

12

0

10 months ago

spi_mem_programmer/372

Small (Q)SPI flash memory programmer in Verilog

22

6

0

10 years ago

osdvu/373

None

22

7

0

2 years ago

Spartan-Mini-NES/374

An FPGA based handheld NES system built around the Spartan 6 and the Spartan Mini development board.

22

3

0

3 days ago

SM3_core/375

None

22

5

0

2 years ago

MIPS-Verilog/376

MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.

22

7

0

8 years ago

tinycpu/377

Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.

22

5

1

5 years ago

Y86-CPU/378

A pipeline CPU in Verilog for the Y86 instruction set.

22

29

0

a month ago

jtag_vpi/379

TCP/IP controlled VPI JTAG Interface.

22

9

0

6 months ago

chacha/380

Verilog 2001 implementation of the ChaCha stream cipher.

21

5

0

9 years ago

pdfparser/381

None

21

17

0

3 years ago

99tsp/382

The 99 Traveling Salespeople Project

21

8

0

8 years ago

Pong/383

Pong game on an FPGA in Verilog.

21

4

1

2 years ago

riscv-soc-cores/384

None

21

4

0

2 years ago

bapi-rv32i/385

A extremely size-optimized RV32I soft processor for FPGA.

21

17

4

1 year, 6 months ago

spi-slave/386

SPI Slave for FPGA in Verilog and VHDL

21

13

1

4 months ago

fifo/387

Generic FIFO implementation with optional FWFT

21

15

1

4 years ago

Nitro-Parts-lib-SPI/388

Verilog SPI master and slave

21

13

0

2 years ago

NPU_on_FPGA/389

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。

21

8

7

6 days ago

corescore/390

CoreScore

21

15

0

1 year, 7 months ago

de10nano_vgaHdmi_chip/391

Test for video output using the ADV7513 chip on a de10 nano board

21

20

0

11 months ago

AMBA_AXI_AHB_APB/392

AMBA bus lecture material

21

14

1

2 years ago

nysa-verilog/393

Verilog Repository for GIT

21

3

0

4 months ago

HDMI-to-FPGA-to-APA102-Pixels/394

Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI.

21

9

3

1 year, 5 months ago

ODIN/395

ODIN online-learning digital spiking neural network (SNN) processor – HDL source code and documentation.

21

0

0

4 months ago

HW-Syn-Lab/396

⚙Hardware Synthesis Laboratory Using Verilog

21

5

2

7 months ago

VGA1306/397

VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!)

21

5

0

7 years ago

usb-de2-fpga/398

Hardware interface for USB controller on DE2 FPGA Platform

21

8

0

a month ago

core_ddr3_controller/399

A DDR3 memory controller in Verilog for various FPGAs

21

0

1

20 days ago

MiSTery/400

Atari ST/STe core for MiST

20

13

0

5 years ago

yafpgatetris/401

Yet Another Tetris on FPGA Implementation